Hardware & Chip Design Projects

Superscalar Out of Order RISC-V Core

Technologies: SystemVerilog, Synopsys DC, Verdi | Duration: Mar 2025 - May 2025

• Engineered an out-of-order RISC-V 32IM processor, feat. EER, GShare predictor, and a split Load-Store unit

• Secured 5th place (50 teams) in design competition with a 1.13 IPC, 33mW power, 240000 μm² area on compression benchmark

• Designed a 2-way superscalar architecture, improved IPC of all benchmarks by ~50% by optimizing multi-word fetch, enabling simultaneous dispatch, multi-commit ROB, pipelined banked icache, and age order issue

• Verified and designed a 4-way set-associative cache by building a custom golden model, DUT driver, scoreboard

Custom SAT Solving ASIC Tapeout

Technologies: SystemVerilog, Synopsys tools, Cadence tools | Duration: May 2025 - Present

• Proposed a SAT Solving ASIC through a custom hardware architecture based on a Mesh Network-on-Chip

• Currently in early stages: will eventually be responsible for algorithmic design, RTL and Physical Design

Real-time Xilinx FPGA 3D Renderer

Technologies: SystemVerilog, C, Vivado, Vitis | Duration: Nov 2024 - Dec 2024

• Designed and implemented an FPGA-based SoC for real-time 3D voxel rendering with user camera inputs

• Integrating a MicroBlaze softcore, custom triangle rasterization FSM, double frame buffer and HDMI video output

• Developed C firmware to accept user input from MAX3421E, allowing for translation/rotation matrix transforms

• Validated the design through comprehensive assert-based simulations and visual verification using bitmap outputs

Pulse Weaver DIP Chip Gesture Audio

Technologies: Analog Circuit Design, Oscilloscope | Duration: Jan 2024 - May 2024

• Developed a gesture-based electronic instrument, using capacitive touch, bend sensors, VCA, VCO, and speaker

Projects

Hardware & Chip Design Projects

Superscalar Out of Order RISC-V Core

Custom SAT Solving ASIC Tapeout

Real-time Xilinx FPGA 3D Renderer

Pulse Weaver DIP Chip Gesture Audio

Software Projects